Exp 2-5 years; Independently execute layout-design of the assigned Analog & Mixed-Signal / RF blocks, which includes floor-planning as per area & top-level, parasitic-aware routing & doing various required physical verifications
Responsible for the on-time delivery of assigned projects with acceptable quality.
Desired Skills and Experience
Analog & Mixed-Signal , RF blocks , layouts & review their work , Contribute to effective project
• Experience in Physical Design implementation
• Should have Played significant role in multiple tape-outs across 90-14nm designs complex block implementation
• Power estimation, planning and analysis (static and dynamic IR, EM)
• Floor planning, placement & congestion, timing closure, CTS, post CTS flow of PV: DRC/LVS/ GDS checks
• Proficient in industry standard EDA tool flows (SNPS or CDN) Optional: Low power.
Develop an IP which will work in conjunction with Video Codec IP to improve the Glass-to-Glass latency of the codec.
Lead role: 5 – 8 yrs range (1 position)
• Own the checklist, preparation and delivery of the release package.
• Manage regressions, monitoring the progress and initial triaging of the failures.
• Compare regression results with the reference results, send the comparison report to development engineers.
• Generate regression environment and share them with the required stakeholders bi-weekly.
• Provide technical guidance; educate team members and coworkers on development and operations.
• Maintain day-to-day management and administration of regression environment.
• Manage CI and tools with team.
• Document and design various processes; update existing processes.
• Follow all best practices and procedures as established by company.
• ASIC/SoC design & implementation experience with specific background in the areas of synthesis, SignOff STA
• Lower technology nodes like 40nm and below till 14nm/10nm.
• Includes definition and development of signoff methodology and corresponding implementation solution
• Flow for STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs.
• Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex, multi-clock, multi-voltage SoC.
• Streamlining the timing signoff criterions, timing analysis methodologies and flows.
• Analyze and incorporate advance timing signoff flows (AOCV, POCV Based STA, IR Drop aware STA) into SoC timing signoff flow.
• Work for Systems and Architecture, SoC Integration, Verification, DFT, Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote teams to address the design challenges in the context of the block, chip, and overall system.
• Concepts of CRPR, clock paths analysis and tweaks to meet timing.
• Multi Corner and MultiMode analysis
• Close timing at SignOff corners covering the entire modes, delay corners for cells and interconnects.